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Extraction of acceptor concentration map from EBIC experiments.

O Marcelot1, P Magnan1

  • 1ISAE-SUPAERO, 10 avenue Edouard Belin, 31055 Toulouse, France.

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|July 3, 2021
PubMed
Summary
This summary is machine-generated.

This study introduces a new method to map acceptor concentration using a single Electron Beam Induced Current (EBIC) image. This technique aids in analyzing semiconductor devices and processed substrates.

Keywords:
CMOSDoping concentrationElectron Beam Induced CurrentImage sensorScanning Electron Microscopy (SEM)Simulation

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Area of Science:

  • Semiconductor device analysis
  • Materials science
  • Doping profile characterization

Background:

  • Accurate control and characterization of two-dimensional doping distributions are crucial for semiconductor device fabrication and performance.
  • Existing methods for mapping doping concentrations can be complex or limited in scope.

Purpose of the Study:

  • To develop a novel methodology for obtaining qualitative maps of acceptor concentration from a single Electron Beam Induced Current (EBIC) image.
  • To enable efficient quality control of processed substrates and specific semiconductor devices.

Main Methods:

  • Utilizing analytical models to determine optimal experimental conditions for EBIC imaging.
  • Employing Technology Computer-Aided Design (TCAD) simulations for validation on realistic device structures.
  • Performing experimental measurements on actual semiconductor devices.

Main Results:

  • The proposed EBIC-based methodology successfully generated qualitative maps of acceptor concentration.
  • TCAD simulations demonstrated the promising potential of the approach.
  • Experimental measurements clearly visualized the epitaxy gradient and the presence of Pwell layers in a device.

Conclusions:

  • The new EBIC imaging methodology provides an effective means for characterizing 2D doping distributions.
  • This technique offers a valuable tool for quality assessment in semiconductor manufacturing.
  • The results confirm the feasibility and utility of the approach for device analysis.