Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC

Area of Science:

• Electrical Engineering
• Computer Engineering
• Integrated Circuit Design

Background:

• System-on-chip (SoC) devices utilize large embedded memories, making them susceptible to various faults.
• Memory faults significantly impact product yield, necessitating effective testing and repair strategies.
• Existing built-in self-repair (BISR) schemes, while effective, can introduce considerable area overhead due to redundancy analysis circuits.

Purpose of the Study:

• To propose and evaluate a novel spare row and column-based BISR method for embedded memories in SoC devices.
• To achieve an optimal repair rate for memory defects with a reduced area overhead.
• To compare the performance of the proposed BISR approach against existing methods.

Main Methods:

• Implementation of a BISR scheme utilizing spare rows and spare columns for memory repair.
• Testing embedded memories for a comprehensive range of fault types.
• Performance evaluation focusing on repair rate, area overhead, and timing.

Main Results:

• The proposed spare row and column-based BISR method demonstrates an optimal repair rate with low area overhead.
• Performance metrics including area overhead, timing, and repair rate were favorably compared to other approaches.
• Increased spare row/column allocation was observed to correlate with higher repair rates and area overhead.

Conclusions:

• The spare row and column-based BISR method offers an effective solution for embedded memory fault repair in SoCs.
• This approach balances high repair efficiency with manageable area overhead.
• The trade-off between repair rate and area overhead necessitates careful consideration of spare resource allocation.