Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES.

Area of Science:

• Computer Engineering
• Cryptography
• Hardware Security

Background:

• Cryptographic algorithms like AES are crucial for data security in connected systems, especially automotive environments.
• Hardware implementations of AES are vulnerable to differential fault analysis, where single faults can corrupt encrypted data.
• Existing fault detection techniques for AES, such as iterative and parallel architectures, have limitations, necessitating exploration of pipelined approaches.

Purpose of the Study:

• To propose a novel hybrid pipeline hardware architecture for the AES algorithm focused on error and fault detection.
• To address the challenges of balancing high throughput, low power consumption, and minimal hardware resources in pipeline designs with fault tolerance.
• To enhance the security of communications in connected vehicles against hardware-based attacks.

Main Methods:

• Developed a hybrid pipeline architecture combining hardware and time redundancy.
• Implemented a pipeline structure for multiple AES ciphering rounds on the same data blocks.
• Integrated a voting module for error detection and a decision tree to optimize the evaluation process.

Main Results:

• The proposed architecture was analyzed and implemented on FPGA technologies.
• Achieved a throughput of 0.479 Gbps on a Virtex-7 FPGA.
• Reported an efficiency of 0.336 Mbps/LUT, demonstrating a balance between performance and resource utilization.

Conclusions:

• The novel hybrid pipeline architecture effectively enhances AES security against fault attacks.
• The design offers a promising solution for secure communications in resource-constrained environments like connected vehicles.
• The approach demonstrates the feasibility of achieving fault tolerance in high-speed cryptographic hardware.