Fixed-Point NLMS and IPNLMS VLSI Architectures for Accurate FECG and FHR Processing

Capturing signals without noise and interference while monitoring the maternal abdomen's fetal electrocardiogram (FECG) is a challenging task. This method can provide fetal monitoring for long hours, not harming the pregnant woman or the fetus. Such non-invasive FECG raw signal suffers from various interference sources as the bio-electric maternal potentials include her ECG component. Therefore, a critical step in the non-invasive FECG is to design the filtering of components derived from the maternal ECG. There is an increasing demand for portable devices to extract a pure FECG signal and to detect fetal heart rate (FHR) with precision. Dedicated CMOS architectures enable higher energy efficiency in portable devices. This paper proposes VLSI architectures dedicated to FECG extraction and FHR processing. Fixed-point architectures for the FECG detection exploring the NLMS (normalized least mean square), IPNLMS (improved proportional NLMS), and three different division VLSI CMOS architectures are designed herein. An architecture based on the Pan-Tompkins algorithm that processes the FECG for extracting the FHR, extending the functionally of the system, is also proposed. The results show that the NLMS and IPNLMS based architectures effectively detect the R-peaks of FECG with a detection accuracy of 92.86% and 93.75%, respectively. The synthesis results shows that our NLMS architecture proposal saves 13.3 % energy, due to a reduction of 279 clock cycles, compared to the state of the art. On the other hand, the IPNLMS algorithm results in +0.89% detection accuracy at the price of 42% additional energy consumption w.r.t NLMS.