3D NoC Low-Power Mapping Optimization Based on Improved Genetic Algorithm.

Area of Science:

• Computer Engineering
• VLSI Design
• Artificial Intelligence

Background:

• Power optimization is critical in network-on-chip (NoC) design.
• Mapping intellectual property (IP) cores to 3D NoC architectures presents significant challenges.
• Traditional genetic algorithms (GAs) suffer from randomness in selection and weak local optimization.

Purpose of the Study:

• To propose an improved genetic algorithm for optimizing IP core mapping in 3D NoC.
• To enhance the convergence and power efficiency of the IP core mapping process.
• To address the limitations of traditional GAs, including randomness and premature convergence.

Main Methods:

• An improved greedy algorithm is integrated for initial population generation to ensure optimal individuals.
• Simulated annealing is incorporated into the crossover operation to improve global optimization and avoid premature convergence.
• The enhanced algorithm is evaluated for its performance in mapping a large number of IP cores (124) to a 3D NoC.

Main Results:

• The proposed algorithm demonstrates superior convergence compared to the traditional genetic algorithm.
• Significant improvements in low power consumption performance were observed.
• For 124 IP cores, the average power consumption was reduced by 42.2%.

Conclusions:

• The enhanced genetic algorithm effectively optimizes IP core mapping in 3D NoC designs.
• The hybrid approach (greedy + simulated annealing + GA) offers better convergence and power efficiency.
• This method provides a faster search for optimal solutions, crucial for complex NoC architectures.