Chip-Level Voltage Controlled Magnetic p-Bits Array with Variation Compensation for Stochastic Neural Network Computation

The increasing computational and energy-efficiency demands of artificial intelligence are driving the development of new computing paradigms based on emerging memory devices. Probabilistic bits (p-bits) based on magnetic tunnel junctions (MTJs), benefiting from energy efficiency, CMOS compatibility, and fast sampling, show broad potential in stochastic neural networks. However, unavoidable device-to-device variations in MTJ switching probabilities hinder the realization of scalable p-bit chips. Here, we integrate a high-density array of voltage-controlled magnetic anisotropy MTJs (VCMA-MTJs) and employ a tail truncation strategy to compensate for their variations in probabilistic switching ranges, enabling chip-level p-bit functionality. Our VCMA-MTJ chip (VM-chip) successfully implements restricted Boltzmann machines (RBM) and deep belief networks (DBN) for image recognition, anomaly detection, image completion, and image generation, demonstrating the practical utility of this chip in stochastic neural networks. Furthermore, we propose a dual-control strategy that tunes both the amplitude and duration of the voltage pulse, significantly enhancing network performance and performing comparably to conventional software-generated pseudo-random numbers. Our work enhances the tolerance of probabilistic computing to variations in MTJ switching probabilities, offering flexibility in device selection and array integration. This approach may provide a promising pathway toward scalable p-bit hardware and cost-effective manufacturing in future probabilistic computing systems.