CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions.

Area of Science:

• Electrical Engineering
• Computer Science
• Artificial Intelligence

Background:

• Traditional neural network design relies on software simulations or commercial CMOS, lacking guaranteed solution quality.
• Optimization methods for objective functions are crucial but often limited in hardware implementation scope.

Purpose of the Study:

• To design and implement a hardware architecture for artificial neural networks (ANNs) based on optimizing n-dimensional objective functions.
• To utilize individual neurons as building blocks for a hardware ANN, focusing on gradient descent for parameter optimization.

Main Methods:

• Designed a 5-3-1 configuration ANN hardware architecture using individual neurons and CMOS operational amplifiers.
• Implemented the design on a 1.2 μm technology integrated circuit, employing the Steepest-Descent learning algorithm for optimization.
• Simulated the integrated circuit using PSpice for digital data classification tasks.

Main Results:

• Achieved a total power consumption of 46.08 mW with nine neurons and 36 CMOS op-amps.
• Demonstrated successful acquisition of synaptic weights and bias values through the Steepest-Descent optimization method.
• Validated the hardware ANN's capability in classifying digital data.

Conclusions:

• The developed hardware architecture effectively implements ANN models using optimized objective functions.
• The gradient descent method successfully generates essential parameters for the neural architecture in a hardware setting.
• This approach offers a viable hardware solution for ANN-based data classification with demonstrated efficiency.