Logic Design and Power Optimization of Floating-Point Multipliers

Area of Science:

• Computer Engineering
• Digital Systems Design
• VLSI Design

Background:

• Multiplication operations in single-precision floating-point arithmetic (IEEE-754 standard) are computationally intensive, leading to high time and power consumption.
• Existing designs face challenges in optimizing these operations for efficiency.

Purpose of the Study:

• To develop an improved single-precision floating-point multiplier that minimizes power consumption and execution time.
• To enhance the throughput of floating-point multiplication operations.

Main Methods:

• Implementation of an expanded Booth-Wallace algorithm for efficient partial product generation.
• Application of symbolic expansion for rounding and prediction of partial products.
• Optimization of partial product accumulation and utilization of pipelining (flowing water) for increased throughput.
• Verification and synthesis simulations using the SMIC-7 nm standard cell process.

Main Results:

• The proposed single-precision floating-point multiplier demonstrates a reduced power share compared to conventional designs.
• The optimizations lead to improved computational efficiency.

Conclusions:

• The expanded Booth-Wallace algorithm, combined with symbolic expansion and pipelining, offers a viable solution for power-efficient floating-point multiplication.
• The developed multiplier design is suitable for high-performance computing applications where power and speed are critical.