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GaAs nanowires on Si nanopillars: towards large scale, phase-engineered arrays
Lucas Güniat1, Lea Ghisalberti1, Li Wang2
1Laboratory of Semiconductor Materials, Institute of Materials, École Polytechnique, Fédérale de Lausanne, 1015 Lausanne, Switzerland.
Nanoscale Horizons
|January 18, 2022
Summary
This study introduces silicon nanopillars for large-scale III-V nanowire growth, improving scalability over traditional methods. Nanopillar oxidation is key to controlling catalyst droplets and enhancing growth yield for wafer-scale manufacturing.
Area of Science:
- Materials Science
- Nanotechnology
- Semiconductor Manufacturing
Background:
- Large-scale fabrication of III-V nanowires requires precise nanoscale patterning, traditionally achieved with slow electron-beam lithography.
- Existing methods face scalability challenges due to feature size requirements (45-60 nm holes) and processing times.
Purpose of the Study:
- To develop a scalable patterning method for wafer-scale III-V nanowire arrays.
- To replace nanoscale holes with silicon nanopillars for improved growth control and manufacturability.
Main Methods:
- Utilized silicon nanopillar arrays instead of nanoscale holes for III-V nanowire growth.
- Employed photolithography techniques compatible with phase-shift and deep ultraviolet (DUV) stepper lithography.
- Investigated nanopillar oxidation to stabilize catalyst droplets and engineer contact angles for optimized growth.
Main Results:
- Demonstrated that silicon nanopillars offer better control over nanowire growth mechanisms and scalability compared to nanoscale holes.
- Identified contact angle engineering, specifically through nanopillar oxidation, as crucial for maximizing yield.
- Achieved a maximum local vertical yield of 67% and a global chip-scale yield of 40% using phase-shift lithography.
Conclusions:
- Silicon nanopillars provide a viable, scalable alternative for large-scale III-V nanowire array fabrication.
- Optimizing nanopillar oxidation and understanding triple phase line behavior are critical for successful nanowire growth.
- Further refinement in semiconductor fabrication processes can potentially increase yields to over 90%, enabling wafer-scale deterministic nanowire engineering.
