Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies.