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A Standard and Reliable Method to Fabricate Two-Dimensional Nanoelectronics
Published on: August 28, 2018
Zero-Bias Photodetection and Opto-Synaptic Plasticity in BP/MoS2 and WS2/PdSe2 van der Waals Heterostructures
Ofelia Durante1, Loredana Viscardi1, Adolfo Mazzotti1
1Department of Physics "E. R. Caianiello", University of Salerno, via Giovanni Paolo II, Fisciano, Salerno 84084, Italy.
Abstract:
van der Waals (vdW) heterostructures assemble atomically thin crystals into defect-free interfaces, where band alignment, interlayer coupling, and built-in electric fields can be engineered for multifunctional, low-power optoelectronics. This Spotlight provides a concise, critical overview of two complementary platforms - BP/MoS2 and WS2/PdSe2 - highlighting how their type-II or type-I band alignment enables optoelectronic operations. In back-gate transistors, both BP/MoS2 and WS2/PdSe2 heterojunctions exhibit transfer curves with high ON/OFF ratios that can reach 107-108 and hysteresis, which is reduced in a vacuum. In BP/MoS2, deterministic stacking and contact/work function engineering stabilize a type-II band offset that supports zero (V ds = 0 V) or low (|V ds| ≤ 5 V) bias operation with fast, dual-time scale photoresponse (from hundreds of ms to ∼1 s) and linear behavior up to 50 μW optical power. Pressure tunes transport mechanisms (from thermionic to band-to-band tunnelling and ohmic), and four-probe data provide a band offset of 68 meV and zero-bias operation at 600 nm, consistent with MoS2-driven visible selectivity. Similarly, WS2/PdSe2 stacks enable visible-band photodetection at low bias, with pressure-tunable transport and photoresponse; the pressure-dependent photocurrent makes them promising for optoelectronic pressure sensing. In a gate-assisted regime (negative V gs in high vacuum), persistent photoconductivity enables opto-synaptic plasticity in WS2/PdSe2 heterojunctions with paired-pulse facilitation (PPF) of 137% and post-tetanic potentiation (PTP) of 300% under 1 s pulse trains. Overall, this Spotlight examines synthesis pathways, interfacial structure, and device-level behavior, and discusses stability, uniformity, and readout compatibility as practical levers for translating single-device demonstrations into reproducible arrays.
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