Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

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Hyangwoo Kim1, Hyeonsu Cho2, Hyeon-Tak Kwak3

  • 1Department of Convergence IT Engineering and Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.

Nanoscale Research Letters
|February 23, 2022
PubMed

Keywords:
Capacitorless 1T DRAMGated-thyristorsMemory array operationMemory disturbanceThree-terminal TRAM

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