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Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory
Hyangwoo Kim1, Hyeonsu Cho2, Hyeon-Tak Kwak3
1Department of Convergence IT Engineering and Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.
Nanoscale Research Letters
|February 23, 2022
Summary
Optimized standby voltages in three-terminal thyristor random-access memory (3-T TRAM) enable continuous data retention without refresh. This low-power nanoscale memory technology shows promise for high-density applications.
Area of Science:
- Materials Science
- Electrical Engineering
- Computer Science
Background:
- Exploring next-generation high-density nanoscale vertical cross-point memory arrays.
- Investigating three-terminal (3-T) thyristor random-access memory (TRAM) for advanced applications.
Purpose of the Study:
- To investigate the effects of standby voltages on 3-T TRAM for superior data retention and low-power operation.
- To propose a memory array operation scheme to mitigate disturbance issues in 3-T TRAM.
Main Methods:
- Thoroughly investigated standby voltages: gate-cathode voltage (VGC,ST) and anode-cathode voltage (VAC,ST).
- Evaluated device performance for data retention and standby current.
- Developed and analyzed a novel 3-T TRAM array operation scheme.
Main Results:
- Optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V achieved continuous data retention without refresh.
- Demonstrated a low standby current of 1.14 pA.
- The proposed array operation scheme effectively minimized disturbances on unselected cells, improving retention to over 10 seconds.
Conclusions:
- Optimized standby voltages significantly enhance data retention characteristics in 3-T TRAM.
- The proposed array operation scheme addresses critical disturbance issues, making 3-T TRAM viable for high-density memory.
- 3-T TRAM offers competitive or superior performance compared to conventional dynamic random-access memory (DRAM).
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