4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source...

Area of Science:

• Semiconductor device fabrication
• Nanotechnology
• Materials science

Background:

• Vertically stacked nanowire transistors offer potential for advanced integrated circuits.
• Optimizing fabrication processes is crucial for achieving high performance in SiGe-based devices.

Purpose of the Study:

• To explore the fabrication and optimize the electrical performance of four-levels vertically stacked Si0.7Ge0.3 channel nanowires gate-all-around transistors.
• To investigate the impact of a source and drain silicide process on device performance.

Main Methods:

• Optimized epitaxial growth and HBr/He/O2 plasma etching for stacked Si0.7Ge0.3/Si fins.
• Utilized a novel ACT@SG-201 solution for Si0.7Ge0.3 channel release.
• Implemented a source and drain silicide process to reduce resistance.

Main Results:

• Achieved excellent device characteristics including a subthreshold slope of 77 mV/dec and an Ion/Ioff ratio of 9 × 10^5.
• The silicide process increased drive current by approximately 6.7 times, reducing source/drain resistance.
• A slight increase in leakage and deterioration of subthreshold slope/Ion/Ioff ratio were observed post-silicidation.

Conclusions:

• The developed fabrication processes enable high-performance stacked Si0.7Ge0.3 nanowire transistors.
• Source and drain silicide is effective in enhancing drive current but requires co-optimization with implantation for leakage reduction.