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Grammatical Evolution of Complex Digital Circuits in SystemVerilog.

Michael Tetteh1, Douglas Mota Dias1,2, Conor Ryan1

  • 1University of Limerick, Limerick, Ireland.

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Summary
This summary is machine-generated.

Evolving complex digital circuits like multipliers is now feasible using Grammatical Evolution (GE) and SystemVerilog at the register-transfer level. This approach overcomes gate-level limitations by employing parameterized modules and corner case testing for efficient circuit generation.

Keywords:
Combinational circuitsCorner case testingEvolutionary design of conventional circuitsEvolvable hardwareGrammatical evolutionHardware description language (HDL)Register transfer level (RTL)Sequential circuitsSystemVerilogVerilog

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Area of Science:

  • Computer Engineering
  • Evolutionary Computation
  • Digital Circuit Design

Background:

  • Evolvable Hardware (EHW) faces challenges in evolving complex circuits due to extensive testing requirements and limited evolvability of representation structures.
  • Gate-level evolution of circuits like a 64-bit multiplier (approx. 33,200 gates) is computationally intensive and difficult.
  • Existing evolutionary approaches struggle with scalability for complex digital circuits.

Purpose of the Study:

  • To develop a more efficient method for evolving complex digital circuits using Grammatical Evolution (GE) and a hardware description language (HDL).
  • To demonstrate the evolution of parameterized circuits at the register-transfer level, enabling scalability and reusability.
  • To introduce an effective corner case testing strategy for evolutionary circuit synthesis, reducing testing time.

Main Methods:

  • Utilized Grammatical Evolution (GE) combined with SystemVerilog, a hardware description language (HDL), to evolve circuits at the register-transfer level.
  • Developed parameterized circuit modules (Adders, Multipliers, Selective Parity, Up-Down Counters) for reusability with varying input sizes.
  • Implemented a corner case testing methodology to optimize the evolutionary testing process, reducing the need for exhaustive testing.

Main Results:

  • Successfully evolved fully functional parameterized Adder, Multiplier, Selective Parity, and Up-Down Counter circuits.
  • Achieved significantly larger circuit complexities (e.g., Multiplier at 10.7k gates) compared to prior state-of-the-art evolutionary methods.
  • Demonstrated the effectiveness of HDL-based evolution and corner case testing in generating complex circuits without standard decomposition methods.

Conclusions:

  • Grammatical Evolution with SystemVerilog at the register-transfer level enables the evolution of complex, parameterized digital circuits.
  • Corner case testing is a viable and efficient strategy for reducing testing overhead in evolutionary circuit design.
  • This approach significantly advances the capabilities of Evolvable Hardware for creating sophisticated digital systems.