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Selectively biased tri-terminal vertically-integrated memristor configuration.

Vasileios Manouras1, Spyros Stathopoulos2, Alex Serb2

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This study introduces a novel vertically stacked memristor configuration. This design enhances device memory and offers potential for surge protection and faster reset times in electronic circuits.

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Area of Science:

  • Materials Science
  • Electrical Engineering
  • Nanotechnology

Background:

  • Memristors offer potential for reconfigurable electronics.
  • Studies on memristor ensembles are limited compared to large arrays.

Purpose of the Study:

  • To propose and investigate a vertically stacked memristor configuration with a shared middle electrode.
  • To explore the compound resistive states and control mechanisms of this novel configuration.
  • To assess the potential applications in enhanced memory, surge protection, and faster reset times.

Main Methods:

  • Fabrication of a vertically stacked memristor with a shared middle electrode.
  • Characterization of individual and combined resistive states.
  • Analysis of switching behaviors under separate and simultaneous control.
  • Evaluation of voltage division properties and surge protection capabilities.

Main Results:

  • Separate switching of individual memristors non-linearly affects the complete device, increasing the resistive state range and number of distinguishable states for enhanced memory.
  • Simultaneous switching creates a voltage divider configuration, enabling surge protection for fragile devices.
  • Simultaneous reset of stacked memristors significantly reduces reset time, beneficial for larger arrays.

Conclusions:

  • The proposed vertically stacked memristor configuration with a shared electrode offers unique insights and functionalities.
  • This configuration enhances device memory capacity and enables novel applications like surge protection.
  • The findings pave the way for more efficient and advanced memristor-based electronic systems.