A Rapid-prototyping CMOS-RRAM Integration Strategy

Area of Science:

• Semiconductor technology
• Materials science
• Electrical engineering

Background:

• Moore's Law faces scaling limitations, necessitating a 'beyond Moore' approach.
• Resistive random-access memories (RRAM) offer innovative solutions for next-generation electronics.
• Integrating RRAM with complementary metal oxide semiconductors (CMOS) presents manufacturing and complexity challenges.

Purpose of the Study:

• To present a cost-effective, rapid-prototyping, and technology-agnostic integration strategy for CMOS-RRAM.
• To detail a systematic approach for combining RRAM with mature CMOS fabrication processes.
• To facilitate the transition from RRAM research and development to volume production.

Main Methods:

• Hybridized wafer-level and multi-reticle processing techniques for CMOS-RRAM integration.
• Leveraging mature front-end-of-line (FEOL) fabrication processes from semiconductor foundries.
• Establishing an in-house RRAM development program for custom CMOS electronics integration.

Main Results:

• A scalable and power-efficient CMOS-RRAM integration strategy is detailed.
• The approach utilizes fully CMOS-compatible and transferable processes.
• Demonstrates a method for combining material/device-level RRAM knowledge with custom CMOS.

Conclusions:

• The proposed integration strategy overcomes challenges in fusing emerging and established semiconductor technologies.
• This method enables seamless RRAM integration, supporting both memory and computation.
• Facilitates a smooth transition from R&D to volume production for advanced electronics.