Jove
Visualize
Contact Us
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Concept Videos

Characteristics of MOSFET01:17

Characteristics of MOSFET

486
Metal-oxide-semiconductor field-effect Transistors, or MOSFETs, play a critical role in electronic circuits. They are primarily utilized for amplifying and switching signals.
Various vital parameters influence their functionality, which is crucial for theory and electronics applications. First, channel dimensions, precisely length, and width, are pivotal. The size of these channels affects the transistor's ability to carry current and switching speeds; shorter channels typically enable...
486
MOSFET Amplifiers01:17

MOSFET Amplifiers

221
The MOSFET, when operating in its active region, functions as a voltage-controlled current source. In this region, the gate-to-source voltage controls the drain current. This principle underlies the operation of the transconductance MOSFET amplifier. The output current is directed through a load resistor to convert this amplifier into a voltage amplifier. The output voltage is then obtained by subtracting the voltage drop across the load resistance from the supply voltage. This process results...
221
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

470
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
470
Biasing of FET01:22

Biasing of FET

364
Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
364
Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

330
Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...
330
Small-Signal Analysis of MOSFET Amplifiers01:23

Small-Signal Analysis of MOSFET Amplifiers

730
In small-signal analysis, a MOSFET transistor amplifier acts as a linear amplifier when operating in its saturation region. The gate-to-source voltage (VGS) of the MOSFET is the sum of the DC biasing voltage and the small time-varying input signal. This combination sets up the operating point and modulates the drain current (ID) that flows from the drain to the source. When a small AC signal is superimposed on the DC bias voltage at the gate, the instantaneous drain current comprises three...
730

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

Microscopic origins of electron trapping in amorphous silicon nitride (a-Si<sub>3</sub>N<sub>4</sub>) and its role in charge-trap flash memory.

Journal of physics. Condensed matter : an Institute of Physics journal·2026
Same author

Reliability and Stability Issues in Bi<sub>2</sub>O<sub>2</sub>Se/β-Bi<sub>2</sub>SeO<sub>5</sub> Field-Effect Transistors.

ACS nano·2026
Same author

Mobile charges in MoS<sub>2</sub>/high-k oxide transistors: from abnormal instabilities to transient negative differential resistance.

Communications engineering·2026
Same author

Quantum tunnelling and leakage current across two-dimensional materials.

Nature materials·2026
Same author

Geometry-Driven Performance Enhancement in h-BN/β-Ga<sub>2</sub>O<sub>3</sub> Heterostructures for Solar-Blind and Polarization-Sensitive Photodetection.

ACS applied materials & interfaces·2026
Same author

Enhanced Zero-Bias Rectification in 1D Metal-Double-Insulator-Graphene Diodes for RF Energy Harvesting.

ACS applied electronic materials·2026

Related Experiment Video

Updated: Sep 5, 2025

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing
06:44

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing

Published on: June 9, 2023

3.3K

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning.

Theresia Knobloch1, Burkay Uzlu2,3, Yury Yu Illarionov1,4

  • 1Institute for Microelectronics, TU Wien, Vienna, Austria.

Nature Electronics
|July 5, 2022
PubMed
Summary

Improving the stability of graphene field-effect transistors involves tuning the Fermi level to minimize charge trapping. This method enhances device performance by reducing hysteresis and drift in electronic devices.

Keywords:
Electrical and electronic engineeringElectronic devicesElectronic properties and devicesTwo-dimensional materials

More Related Videos

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
15:47

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Published on: November 1, 2013

16.4K
Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
14:16

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

7.8K

Related Experiment Videos

Last Updated: Sep 5, 2025

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing
06:44

Tuning Oxide Properties by Oxygen Vacancy Control During Growth and Annealing

Published on: June 9, 2023

3.3K
Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
15:47

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Published on: November 1, 2013

16.4K
Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy
14:16

Fabrication of Schottky Diodes on Zn-polar BeMgZnO/ZnO Heterostructure Grown by Plasma-assisted Molecular Beam Epitaxy

Published on: October 23, 2018

7.8K

Area of Science:

  • Materials Science
  • Condensed Matter Physics
  • Electrical Engineering

Background:

  • Two-dimensional (2D) semiconductor devices face stability issues due to charge carrier interaction with insulator defects.
  • Amorphous gate oxides (e.g., SiO2, HfO2) in field-effect transistors (FETs) cause hysteresis and drift, limiting circuit stability.
  • Graphene-based FETs are particularly susceptible to these stability limitations.

Purpose of the Study:

  • To enhance the electrical stability of graphene-based field-effect transistors (FETs).
  • To investigate the role of Fermi-level tuning in mitigating charge trapping at the semiconductor-insulator interface.
  • To demonstrate a method for improving device reliability without altering the total defect density in the gate oxide.

Main Methods:

  • Utilized Fermi-level tuning in graphene channel engineering.
  • Controlled the energetic alignment between channel charge carriers and defect bands in amorphous aluminum gate oxide.
  • Analyzed charge trapping sensitivity to Fermi level alignment with insulator defect bands.

Main Results:

  • Achieved improved device stability in graphene FETs with amorphous gate oxides.
  • Demonstrated that Fermi-level tuning minimizes electrically active border traps.
  • Showed that charge trapping is highly sensitive to the energetic alignment between the channel Fermi level and insulator defect bands.

Conclusions:

  • Fermi-level tuning is an effective strategy for enhancing the stability of 2D semiconductor devices.
  • Minimizing active border traps through energetic alignment is key to reducing hysteresis and drift.
  • This approach offers a pathway to more reliable electronic devices based on 2D materials and amorphous dielectrics.