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Published on: June 8, 2018
A Hardware-Friendly Low-Bit Power-of-Two Quantization Method for CNNs and Its FPGA Implementation.
Xuefu Sui1,2,3, Qunbo Lv1,2,3, Yang Bai1,2,3
1Aerospace Information Research Institute, Chinese Academy of Sciences, No. 9 Dengzhuang South Road, Haidian District, Beijing 100094, China.
Global Sign-based Network Quantization (GSNQ) offers an efficient low-bit quantization method for Convolutional Neural Networks (CNNs). This approach reduces hardware resource usage on FPGAs while maintaining or improving model accuracy, enabling industrial applications.
Area of Science:
- Computer Science
- Artificial Intelligence
- Machine Learning
Background:
- Convolutional Neural Networks (CNNs) face challenges in balancing accuracy, efficiency, and hardware resource consumption (DSPs, RAMs on FPGAs), limiting their industrial applicability.
- Existing quantization methods struggle to meet the stringent demands of industrial applications for low-bit CNNs.
Purpose of the Study:
- To propose an innovative low-bit power-of-two quantization method, Global Sign-based Network Quantization (GSNQ), to address the resource and accuracy limitations of CNNs.
- To develop a novel convolutional algorithm for efficient FPGA deployment of quantized CNN models.
- To validate the effectiveness of GSNQ in reducing accuracy loss and improving hardware adaptability.
Main Methods:
- Introduced Global Sign-based Network Quantization (GSNQ), a method that quantizes weights based on their sign to expand the value range.
- Developed a fine-grained, multi-scale global retraining strategy to mitigate accuracy degradation from low-bit quantization.
- Proposed a novel convolutional algorithm replacing multiplication with shift operations for FPGA implementation.
Main Results:
- GSNQ demonstrated superior accuracy compared to existing methods across various CNN architectures (LeNet-5, AlexNet, VGG-Net, ResNet, GoogLeNet).
- Achieved "lossless" quantization (accuracy higher than baseline) in most low-bit scenarios.
- FPGA experiments confirmed the convolutional algorithm's minimal DSP usage and low occupancy of LUTs/FFs, enhancing computational parallelism and demonstrating strong hardware adaptability.
Conclusions:
- GSNQ effectively reduces hardware resource requirements for CNNs on FPGAs without compromising accuracy, often improving it.
- The proposed method and algorithm provide a viable solution for deploying efficient and accurate CNNs in industrial settings.
- GSNQ offers theoretical and experimental validation for the practical industrial application of low-bit quantized CNNs.
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