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A Comparison of Surrogate Behavioral Models for Power Amplifier Linearization under High Sparse Data.

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This study introduces a feature extraction method for power amplifier (PA) modeling, addressing sparse data challenges. The approach ensures reliable validation and low complexity for digital predistortion (DPD) applications.

Keywords:
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Area of Science:

  • Electrical Engineering
  • Signal Processing
  • Machine Learning

Background:

  • Accurate power amplifier (PA) behavioral modeling is crucial for mitigating nonlinearities, especially with digital predistortion (DPD) for linearization.
  • Validating PA models under signal conditioning and transmission restrictions requires a robust framework.

Purpose of the Study:

  • To develop a framework for validating PA modeling figures of merit under signal conditioning and transmission restrictions.
  • To introduce a feature extraction concept for heuristic target approach modeling, addressing sparse data in amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) models.

Main Methods:

  • An FPGA-based testbed was developed to measure wide-band PA behavior using LTE-based 64-QAM OFDM signals.
  • A feature extraction concept was introduced to manage sparse data issues in AM-AM/AM-PM model extraction.
  • Models were compared against regression tree (RT), random forest (RF), and cubic-spline (CS) for accuracy and complexity.

Main Results:

  • Experimental results demonstrated model performance in high sparse data regimes.
  • The proposed models showed reliable validation and low complexity compared to RT, RF, and CS.
  • Figures of merit included PAPR, CCDF, coefficients extraction, NMSE, and execution time.

Conclusions:

  • The presented models, including machine learning (ML)-based and CS interpolated, offer effective solutions for high sparse data scenarios.
  • The CS interpolated models demonstrated efficacy in prediction methods with lower convergence times and complexities.
  • The study provides a reliable validation framework for PA modeling with reduced hardware complexity.