Efficient Hardware Accelerator Design of Non-Linear Optimization Correlative Scan Matching Algorithm in 2D LiDAR SLAM...

Area of Science:

• Robotics
• Computer Vision
• Hardware Acceleration

Background:

• Simultaneous Localization and Mapping (SLAM) is crucial for mobile robots to map unknown environments and track their position.
• Correlative Scan Matching (CSM) is a key algorithm for estimating robot pose in SLAM.
• Existing methods often require significant computational resources.

Purpose of the Study:

• To develop an efficient Non-linear Optimization Correlative Scan Matching (NLO-CSM) algorithm.
• To design a hardware accelerator for the NLO-CSM algorithm tailored for 2D LiDAR SLAM.
• To reduce computational demands and energy consumption while maintaining high accuracy.

Main Methods:

• Combined non-linear optimization with the CSM algorithm to create NLO-CSM.
• Implemented NLO-CSM on an FPGA utilizing pipeline processing and module reusing.
• Evaluated performance using FPGA and simulated ASIC implementations.

Main Results:

• FPGA implementation achieved 8.98 ms per frame at 0.79 W power consumption.
• Outperformed ARM-A9 CPU by 92.74% in speed and 90.71% in energy efficiency.
• ASIC implementation projected 5.94 ms and 0.06 mJ per scan, demonstrating significant resource and energy savings.

Conclusions:

• The NLO-CSM hardware accelerator offers a highly efficient solution for scan matching in SLAM.
• Achieved substantial improvements in speed, energy efficiency, and resource utilization compared to CPU and prior hardware designs.
• The design is well-suited for power-efficient and resource-limited mobile and micro robot applications.