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FPGA Implementation of the Chirp-Scaling Algorithm for Real-Time Synthetic Aperture Radar Imaging.

Jaehyeon Lee1, Dongmin Jeong2, Seongwook Lee1

  • 1School of Electronics and Information Engineering, Korea Aerospace University, Goyang-si 10540, Republic of Korea.

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|January 21, 2023
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Summary
This summary is machine-generated.

This study introduces a hardware accelerator for Synthetic Aperture Radar (SAR) imaging using a modified Chirp Scaling Algorithm (CSA). The FPGA-based processor significantly speeds up real-time SAR image processing, making it suitable for small drone systems.

Keywords:
chirp-scaling algorithm (CSA)field programmable gate array (FPGA)real-time processingsynthetic aperture radar (SAR)systolic array processor

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Area of Science:

  • Radar Systems Engineering
  • Signal Processing
  • Embedded Systems Design

Background:

  • Synthetic Aperture Radar (SAR) systems are crucial for imaging, but real-time processing of SAR data using algorithms like Chirp Scaling Algorithm (CSA) is computationally intensive.
  • Existing CSA implementations face challenges with long execution times, hindering real-time applications, especially for miniaturized SAR systems on drones.
  • There is a growing need for efficient SAR processors that meet stringent area and power constraints for portable platforms.

Purpose of the Study:

  • To develop a hardware accelerator for the Chirp Scaling Algorithm (CSA) to enhance real-time SAR imaging processing speed.
  • To propose and implement a modified CSA flow optimized for hardware acceleration on Field-Programmable Gate Arrays (FPGAs).
  • To design an area-efficient SAR processor suitable for small, power-constrained SAR systems.

Main Methods:

  • Proposed a modified Chirp Scaling Algorithm (CSA) flow by altering the transpose operation sequence for simplified processing.
  • Designed a hardware accelerator on a Xilinx UltraScale+ MPSoC FPGA using Verilog-HDL, featuring a shared multiplier for Fast Fourier Transform (FFT) and phase compensation.
  • Implemented the CSA-based SAR processor, supporting FFT and phase compensation operations.

Main Results:

  • Achieved significant speed improvement for SAR image processing compared to a conventional microprocessor.
  • Demonstrated a 136.2-fold increase in processing speed for a 4096 × 4096-pixel image when comparing the FPGA implementation to an ARM Cortex-A53 microprocessor.
  • The hardware accelerator achieved area efficiency by sharing computational resources, simplifying the overall data flow.

Conclusions:

  • The proposed FPGA-based SAR processor effectively accelerates the modified CSA flow, addressing the real-time processing demands of SAR imaging.
  • The design is suitable for miniaturized SAR systems, offering a balance of performance, area, and power efficiency for drone applications.
  • The shared multiplier design contributes to area efficiency and simplified hardware architecture, validating the proposed approach for practical SAR system development.