A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation.

Area of Science:

• Integrated Circuit Design
• Low-Power Electronics
• Semiconductor Devices

Background:

• Voltage references are critical components in electronic systems, requiring high stability and low power consumption.
• Existing designs often struggle with line sensitivity and power efficiency, especially in advanced CMOS processes.
• The drain-induced barrier-lowering (DIBL) effect in transistors degrades voltage reference performance.

Purpose of the Study:

• To design and simulate an ultra-low-power voltage reference circuit.
• To minimize line sensitivity and improve power supply rejection ratio (PSRR).
• To achieve high thermal stability for the reference voltage.

Main Methods:

• A two-transistor (2-T) voltage reference core was designed in 180 nm CMOS technology.
• A novel current source biasing technique was employed to compensate for the DIBL effect.
• Monte Carlo simulations were used to evaluate performance across process variations.

Main Results:

• Achieved a near-zero line sensitivity of 0.035 %/V over a 0.6-1.8 V supply range.
• Generated a stable reference voltage of 307.8 mV with an ultra-low power consumption of 21.4 pW.
• Demonstrated a power supply rejection ratio (PSRR) of -54 dB at 100 Hz and a temperature coefficient of 24.8 ppm/°C from -20 to 80 °C.
• The circuit occupies a small area of 0.003 mm².

Conclusions:

• The proposed compensated voltage reference effectively mitigates DIBL effects, leading to superior line sensitivity.
• The design offers an excellent trade-off between low power consumption, high accuracy, and stability.
• This ultra-low-power voltage reference is suitable for power-constrained applications in integrated circuits.