Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) are crucial for power electronics.
• Achieving low ohmic contact resistance and high reliability in E-mode p-GaN gate HEMTs remains a challenge.
• CMOS-compatible fabrication processes are desired for integrating GaN devices.

Purpose of the Study:

• To develop a low ohmic contact resistance process for 650 V E-mode p-GaN gate HEMTs.
• To enhance the reliability and stability of these GaN power devices.
• To demonstrate a viable method for CMOS-compatible GaN power device fabrication.

Main Methods:

• Insertion of an amorphous silicon (a-Si) assisted layer between the ohmic contact and GaN.
• Annealing the fabricated device at 550 °C.
• Applying high gate bias stress at 150 °C for 10^-2 s to assess threshold voltage stability and time to failure (TTF).

Main Results:

• Achieved a low contact resistance of approximately 0.6 Ω-mm.
• Reduced threshold voltage shifting from -0.85 V to -0.74 V under stress conditions.
• Demonstrated a 100-fold improvement in high-temperature gate bias (HTGB) TTF, indicating enhanced device reliability.

Conclusions:

• The amorphous silicon-assisted ohmic contact process significantly improves GaN HEMT performance and reliability.
• A low thermal budget process is effective in enhancing device stability and lifetime.
• This method offers a promising pathway for CMOS-compatible GaN power device manufacturing.