An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor

Area of Science:

• Electrical Engineering
• Semiconductor Devices
• Image Sensors

Background:

• Lateral Overflow Integration Capacitor (LOFIC) complementary metal oxide semiconductor (CMOS) image sensors enable high-dynamic-range (HDR) imaging by combining low-conversion-gain (LCG) and high-conversion-gain (HCG) signals.
• Conventional LOFIC-CMOS sensors require a two-channel read-out chain for inverted polarity LCG and HCG signals, increasing chip area.

Purpose of the Study:

• To develop an area-efficient LOFIC-CMOS image sensor by presenting a single-channel read-out circuit.
• To enable processing of both HCG and LCG signals within a single read-out chain.

Main Methods:

• Designed an up/down double-sampling circuit incorporating an inverting amplifier for HCG signals and a non-inverting attenuator for LCG signals.
• Fabricated a test chip using a 0.18 μm CMOS process with a metal-insulator-metal (MIM) capacitor.

Main Results:

• Achieved a readout noise of 130 μVrms for the HCG signal and 1.19 V for the LCG input window.
• The single-channel read-out chain reduced the area by half compared to traditional two-channel designs.
• Demonstrated performance equivalent to 103 dB dynamic range.

Conclusions:

• The proposed one-channel read-out circuit effectively reduces the area of LOFIC-CMOS image sensors.
• This approach maintains high dynamic range performance while simplifying the sensor architecture.