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A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory.

Jianquan Jia1,2, Lei Jin1,2, Xinlei Jia1,2

  • 1Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.

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Summary
This summary is machine-generated.

Z-interference in 3D NAND flash memory worsens with scaling. A new programming method reduces this interference by lowering adjacent cell pass voltage, significantly improving reliability for scaled devices.

Keywords:
3D NANDadjacent gate pass voltagecell-to-cell z-interference programcharge-trapping memory

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Area of Science:

  • Semiconductor Device Physics
  • Materials Science

Background:

  • Cell-to-cell z-interference is a critical reliability issue in 3D NAND charge-trap memory, exacerbated by shrinking gate length (Lg) and gate spacing length (Ls).
  • This phenomenon poses a significant challenge to the continued scaling of 3D NAND technology.

Purpose of the Study:

  • To investigate the underlying mechanisms of z-interference during the programming operation in 3D NAND flash memory.
  • To propose and validate a novel programming scheme to mitigate z-interference and improve cell reliability.

Main Methods:

  • Utilized Technology Computer-Aided Design (TCAD) simulations to model and analyze z-interference mechanisms.
  • Employed silicon data verification to confirm simulation findings and assess the effectiveness of the proposed scheme.

Main Results:

  • Identified inter-cell trapped charges, modulated during programming, as a key contributor to z-interference.
  • The proposed scheme, reducing the pass voltage (Vpass) of adjacent cells, achieved a 40.1% suppression of the threshold voltage (Vth) shift in erased cells for Lg/Ls = 31/20 nm.
  • Analysis provided insights into optimizing the balance between program disturbance and z-interference for scaled Lg-Ls.

Conclusions:

  • The novel programming scheme effectively suppresses z-interference in 3D NAND flash memory.
  • This approach offers a viable solution for enhancing the reliability of scaled 3D NAND devices.
  • Further analysis supports the optimization of programming strategies for future NAND flash scaling.