A Low-Cost Measurement Methodology for LiDAR Receiver Integrated Circuits

Area of Science:

• Integrated Circuit Design
• Optical Sensing Technologies
• Metrology and Measurement Science

Background:

• LiDAR systems rely on precise timing measurements for range estimation.
• Traditional LiDAR receiver ICs suffer from walk errors due to signal degradation through analog front-end (AFE) circuits and amplifiers.
• Existing walk error compensation methods are often complex and increase chip area.

Purpose of the Study:

• To propose a simplified and cost-effective test methodology for LiDAR receiver ICs.
• To address and mitigate the inherent walk error issue in LiDAR signal processing.
• To enable easier and more accurate range measurements in LiDAR applications.

Main Methods:

• Implementation of a high-speed buffer and variable delay cells preceding the Time-to-Digital Converter (TDC).
• Ensuring START and STOP pulses exhibit similar pulse shapes to prevent walk errors.
• Utilizing variable delay cells to precisely control the time interval between pulses.

Main Results:

• The proposed methodology effectively eliminates walk errors in LiDAR receiver ICs.
• Demonstrated easier and more accurate measurement results on test chips fabricated in a 180-nm CMOS process.
• The new approach avoids complex algorithms and reduces the need for extra chip area.

Conclusions:

• The presented test methodology offers a simpler, lower-cost solution for testing LiDAR receiver ICs.
• This innovation enhances the accuracy and ease of range measurement in LiDAR systems.
• The successful demonstration on test chips validates the effectiveness of the proposed approach.