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Related Concept Videos

MOS Capacitor01:25

MOS Capacitor

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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
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Biasing of FET01:22

Biasing of FET

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Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
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Characteristics of MOSFET01:17

Characteristics of MOSFET

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Metal-oxide-semiconductor field-effect Transistors, or MOSFETs, play a critical role in electronic circuits. They are primarily utilized for amplifying and switching signals.
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MOSFET: Depletion Mode01:20

MOSFET: Depletion Mode

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Depletion-mode MOSFETs represent a unique subset of MOSFET technology, functioning fundamentally differently from their enhancement-mode counterparts. Unlike enhancement MOSFETs, which require a positive gate-source voltage (Vgs) to turn on, depletion-mode MOSFETs are inherently conductive and "normally on" devices.
The primary characteristic of depletion-mode MOSFETs is their ability to conduct current between the drain and source terminals without gate bias. This inherent conductivity...
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Field Effect Transistor01:29

Field Effect Transistor

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Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
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Biasing of Metal-Semiconductor Junctions01:27

Biasing of Metal-Semiconductor Junctions

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Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
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Updated: Jul 16, 2025

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Eliminating Ferroelectric Hysteresis in All-Two-Dimensional Gate-Stack Negative-Capacitance Transistors.

Hui Quan1,2, Dehuan Meng2, Xuezhou Ma2

  • 1Hunan Institute of Advanced Sensing and Information Technology, Xiangtan University, Xiangtan 411105, China.

ACS Applied Materials & Interfaces
|September 18, 2023
PubMed
Summary
This summary is machine-generated.

Negative-capacitance field-effect transistors (NC FETs) using MoS2 and CuInP2S6 achieve a steep subthreshold swing (SS) below 60 mV/decade. Inserting h-BN layers improved performance, reducing hysteresis and boosting transconductance.

Keywords:
CuInP2S6MoS2NC FETh-BNhysteresissubthreshold swing

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Area of Science:

  • Materials Science
  • Semiconductor Physics
  • Device Engineering

Background:

  • Boltzmann distribution limits field-effect transistor (FET) subthreshold swing (SS) below 60 mV/decade at room temperature, hindering lower operating voltages and power consumption.
  • Negative-capacitance FETs (NC FETs) offer a potential solution by utilizing ferroelectric materials to amplify gate voltage, aiming to overcome the SS limit.

Purpose of the Study:

  • To investigate the performance of MoS2-based NC FETs incorporating a CuInP2S6 ferroelectric layer.
  • To explore the impact of inserting hexagonal boron nitride (h-BN) interlayers on device performance, specifically SS and hysteresis.
  • To analyze the underlying mechanisms of voltage amplification and transconductance enhancement in capacitance-matched NC FETs.

Main Methods:

  • Fabrication of MoS2 NC FETs with a CuInP2S6 ferroelectric layer.
  • Integration of h-phase boron nitride (h-BN) interlayers of varying thicknesses.
  • Electrical characterization including on/off ratio, SS, hysteresis, and transconductance measurements.

Main Results:

  • The MoS2 NC FET with CuInP2S6 exhibited a high on/off ratio (10^8) and a very steep SS (6 mV/decade) over 4 orders of magnitude, albeit with significant hysteresis (>500 mV).
  • Insertion of a suitable h-BN layer improved capacitance matching between the dielectric and ferroelectric layers, reducing hysteresis to 5 mV and achieving an SS of 62 mV/decade.
  • Hysteresis-free NC FETs under capacitance-matched conditions did not show predicted steep-slope behavior but acted as effective transconductance boosters, achieving over 20x amplification.

Conclusions:

  • Capacitance matching is crucial for optimizing NC FET performance, enabling reduced hysteresis and improved switching behavior.
  • While hysteresis-free operation under matched conditions doesn't yield ultra-steep SS, it effectively boosts transconductance, offering a viable pathway for power-efficient electronics.
  • This work demonstrates a practical approach to enhance transistor performance beyond the Boltzmann limit using ferroelectric negative capacitance effects.