Addressable superconductor integrated circuit memory from delay lines

Area of Science:

• Solid-state physics
• Electrical engineering
• Computer science

Background:

• Superconductor electronics are being revisited for energy-efficient computing and quantum control.
• Scalable superconducting memory remains a significant technological challenge.
• Existing approaches focus on storage cell miniaturization.

Purpose of the Study:

• To present a novel superconducting delay-line memory system as an alternative to cell miniaturization.
• To leverage the properties of superconducting passive transmission lines for memory applications.
• To develop a scalable and energy-efficient superconducting memory solution.

Main Methods:

• Exploiting minimal attenuation and dispersion of superconducting passive transmission lines.
• Designing a fully superconducting delay-line memory architecture.
• Utilizing the MIT Lincoln Laboratory SC2 fabrication process.

Main Results:

• Demonstrated data densities in the tens of Megabits per square centimeter (Mbit/cm²).
• Achieved operating speeds between 20 and 100 GHz.
• Exhibited ± 24% and ± 13% bias margins.
• Circulating design allows for minimal control circuitry and eliminates data splitting/merging.

Conclusions:

• The superconducting delay-line memory system offers a promising alternative for scalable superconducting memory.
• The design enables inexpensive implementations of sequential access and content-addressable memories.
• Future fabrication process advancements suggest potential for hundreds of Mbit/cm² data densities and beyond.