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Biasing of FET01:22

Biasing of FET

300
Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...
300
Field Effect Transistor01:29

Field Effect Transistor

439
Field-effect transistors (FETs) are integral to electronic circuits and distinguished by their three-terminal setup: the gate, drain, and source. These transistors operate as unipolar devices, which utilize either electrons or holes as charge carriers, in contrast to bipolar transistors, which use both types of carriers. The primary function of the FET is to modulate the flow of these carriers from the source to the drain through a channel. The voltage difference between the gate and source...
439
MOS Capacitor01:25

MOS Capacitor

815
A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
The metal gate is typically made from highly conductive materials such as aluminum or polysilicon. Beneath the metal gate lies a thin layer of...
815
MOSFET: Enhancement Mode01:22

MOSFET: Enhancement Mode

363
Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...
363
Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

794
In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
794
Metal-Semiconductor Junctions01:24

Metal-Semiconductor Junctions

360
The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...
360

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Related Experiment Video

Updated: Jul 14, 2025

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx
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In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

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First demonstration of in-memory computing crossbar using multi-level Cell FeFET.

Taha Soliman1, Swetaki Chatterjee2,3, Nellie Laleni4

  • 1Robert Bosch GmbH, Renningen, Germany. taha.soliman@de.bosch.com.

Nature Communications
|October 10, 2023
PubMed
Summary
This summary is machine-generated.

This study introduces a novel in-memory computing (IMC) crossbar macro using multi-level ferroelectric field-effect transistor (FeFET) cells for efficient multi-bit multiply and accumulate (MAC) operations, achieving high accuracy and performance.

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Area of Science:

  • Semiconductor device physics
  • Artificial intelligence hardware
  • Computer architecture

Background:

  • Artificial intelligence (AI) advancements necessitate efficient computing and memory solutions.
  • In-memory computing (IMC) architectures offer a promising approach to address these challenges.
  • Ferroelectric field-effect transistors (FeFETs) are emerging as key components for advanced memory and computing.

Purpose of the Study:

  • To introduce a novel IMC crossbar macro employing a multi-level FeFET cell.
  • To enable multi-bit multiply and accumulate (MAC) operations using a single FeFET per resistor (1FeFET-1R) cell.
  • To minimize device variability effects on computational accuracy in IMC.

Main Methods:

  • Design and fabrication of a 1FeFET-1R crossbar macro using 28 nm HKMG technology FeFET devices.
  • Leveraging the electrical characteristics of stored data within FeFETs for MAC operations.
  • Encoding MAC results in activation time and accumulated current, bypassing traditional resistive memory approaches.

Main Results:

  • Experimental validation demonstrating high accuracy for handwriting recognition (96.6%) and image classification (91.5%) without retraining.
  • Achieved exceptional energy efficiency of 885.4 TOPS/W, nearly doubling existing designs.
  • Successfully implemented a complete MAC operation macro using multi-state FeFET cells, maintaining crossbar density.

Conclusions:

  • The proposed FeFET-based IMC macro offers a viable solution for high-performance, low-power AI hardware.
  • This work represents a significant advancement in realizing dense, efficient in-memory computing architectures.
  • The novel approach demonstrates the potential of multi-level FeFET cells for future AI accelerators.