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Related Concept Videos

Parallel Processing01:20

Parallel Processing

164
The brain processes sensory information rapidly due to parallel processing, which involves sending data across multiple neural pathways at the same time. This method allows the brain to manage various sensory qualities, such as shapes, colors, movements, and locations, all concurrently. For instance, when observing a forest landscape, the brain simultaneously processes the movement of leaves, the shapes of trees, the depth between them, and the various shades of green. This enables a quick and...
164
Clamper Circuit01:14

Clamper Circuit

447
A clamper circuit, also known as a DC restorer, represents a specialized variant of the rectifier circuit, notable for its method of taking the output across the diode rather than the capacitor. This configuration lends to several distinctive applications, particularly in handling square wave inputs.
Within this circuit, the diode's orientation prompts the capacitor to charge up to the level of the most negative peak of the input signal. Upon reaching this state, the diode ceases to...
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Accelerators01:17

Accelerators

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Accelerators in concrete serve as admixtures to speed up the hardening process, enabling the concrete to achieve early strength faster. Although accelerators do not necessarily impact the time it takes concrete to set, they reduce this time in practice. A common accelerator is calcium chloride, which is particularly useful for hastening early strength development in cold weather or for rapid repair jobs that require quick heat generation after mixing.
The effectiveness of calcium chloride can...
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Reducing Line Loss01:18

Reducing Line Loss

156
In a three-phase circuit, line loss is an indicator of energy dissipated as heat due to the resistance of transmission lines. To address this, incorporating transformers into the system—a step-up transformer at the source and a step-down transformer at the load—is a strategic solution. Two three-phase transformers are introduced to improve this.
With a step-up transformer at the source, the voltage is increased, thereby reducing the current in the transmission lines since power loss...
156
Clipper Circuit01:18

Clipper Circuit

458
A clipper circuit is a fundamental wave-shaping device that harnesses the unique properties of diodes to alter and control waveform characteristics. This technology is widely used in electronic devices, especially in television and radar communication systems, where it enhances waveform modulation in both transmitters and receivers.
The operation of a clipper circuit can be exemplified by analyzing a dual-clipper configuration setup that integrates two ideal diodes, each paired with a biasing...
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Block Diagram Reduction01:22

Block Diagram Reduction

221
The process of deriving the transfer function of a control system often involves reducing its block diagram to a single block. This simplification can be achieved through a series of strategic operations, including relocating branch points and comparators. These operations preserve the overall function of the system while allowing for easier manipulation and combination of blocks.
The first step in this process is the identification and relocation of a branch point. A branch point, where a...
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AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.

Hyeong-Ju Kang1, Byung-Do Yang2

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This study introduces memory-reduction techniques for Convolutional Neural Networks (CNNs) in EdgeAI and TinyML. These methods enable efficient CNN implementation on resource-constrained devices using only on-chip memory.

Keywords:
CNN acceleratorconvolutional neural networkspruning

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Area of Science:

  • Computer Science
  • Artificial Intelligence
  • Embedded Systems

Background:

  • Convolutional Neural Networks (CNNs) are vital for EdgeAI and TinyML but demand significant memory.
  • External memory requirements hinder the feasibility of CNNs in resource-limited EdgeAI and TinyML applications.

Purpose of the Study:

  • To propose novel memory-reduction methods for CNNs at both algorithmic and architectural levels.
  • To enable the implementation of performant CNNs using only the on-chip memory of practical devices.

Main Methods:

  • Implemented accelerator-aware pruning to reduce weight memory.
  • Proposed a stream-based line-buffer architecture for activation memory reduction.
  • Utilized a pipelined approach with dedicated layer blocks and line buffers instead of frame buffers.

Main Results:

  • Successfully reduced intermediate data storage size.
  • Demonstrated the implementation of object-detection CNNs (MobileNetV1/V2, SSDLite variant) on a low-end FPGA.
  • Achieved implementation without requiring external memory.

Conclusions:

  • The proposed memory-reduction techniques are effective for deploying CNNs in resource-constrained EdgeAI and TinyML environments.
  • On-chip memory implementation of CNNs is feasible for practical applications like object detection on low-end FPGAs.