DTCO optimizes critical path nets to improve chip performance with timing-aware OPC in deep ultraviolet lithography

Area of Science:

• Semiconductor Manufacturing
• Integrated Circuit Design
• Lithography Technology

Background:

• Pitch scaling in semiconductor manufacturing faces increasing costs and complexity.
• Lithography is a key driver of dimensional scaling in integrated circuits.
• Process variation (PV) and edge placement error (EPE) impact chip performance and yield.

Purpose of the Study:

• To propose a Design Technology Co-optimization (DTCO) flow to mitigate PV band and EPE.
• To reduce the impact of process variations and edge placement errors in high-performance processors.
• To enhance chip performance by optimizing critical design paths.

Main Methods:

• Digital back-end design of a high-performance processor and generation of a test layout.
• Timing analysis to identify critical path nets affecting chip performance.
• Development of a timing-aware optimized optical proximity correction (OPC) method.

Main Results:

• The proposed timing-aware OPC method adjusts critical path net merit points and sub-resolution assistant features.
• Tighter EPE specifications and denser merit points/breakpoints were applied to critical paths.
• Significant reduction in EPE and a slight decrease in PV band were achieved.

Conclusions:

• The proposed DTCO flow effectively reduces EPE and PV band while maintaining process windows.
• This approach offers a viable strategy for managing complexity and cost in advanced semiconductor manufacturing.
• Optimized OPC based on timing criticality improves overall chip performance and manufacturability.