Comprehensive understanding of electron mobility and superior performance in sub-10 nm DG ML tetrahex-GeC₂ n-type...

In this study, we have investigated the electron mobility of monolayered (ML) tetrahex-GeC₂ by solving the linearized Boltzmann transport equation (BTE) with the normalized full-band relaxation time approximation (RTA) using density functional theory (DFT). Contrary to what the deformation potential theory (DPT) suggested, the ZA acoustic mode was determined to be the most restrictive for electron mobility, not the LA mode. The electron mobility at 300 K is 803 cm² (V s)^-1, exceeding the 400 cm² (V s)^-1 of MoS₂ which was calculated using the same method and measured experimentally. The ab initio quantum transport simulations were performed to assess the performance limits of sub-10 nm DG ML tetrahex-GeC₂ n-type MOSFETs, including gate lengths (L_g) of 3 nm, 5 nm, 7 nm, and 9 nm, with the underlap (UL) effect considered for the first two. For both high-performance (HP) and low-power (LP) applications, their on-state currents (I_on) can meet the requirements of similar nodes in the ITRS 2013. In particular, the I_on is more remarkable for HP applications than that of the extensively studied MoS₂. For LP applications, the I_on values at L_g of 7 and 9 nm surpass those of arsenene, known for having the largest I_on among 2D semiconductors. Subthreshold swings (SSs) as low as 69/53 mV dec^-1 at an L_g of 9 nm were observed for HP/LP applications, and 73 mV dec^-1 at an L_g of 5 nm for LP applications, indicating the excellent gate control capability. Moreover, the delay time τ and power dissipation (PDP) at L_g values of 3 nm, 5 nm, 7 nm, and 9 nm are all below the upper limits of the ITRS 2013 HP/LP proximity nodes and are comparable to or lower than those of typical 2D semiconductors. The sub-10 nm DG ML tetrahex-GeC₂ n-type MOSFETs can be down-scaled to 9 nm and 5 nm for HP and LP applications, respectively, displaying desirable I_on, delay time τ, and PDP in the ballistic limit, making them a potential choice for sub-10 nm transistors.