Efficient FPGA Implementation of Convolutional Neural Networks and Long Short-Term Memory for Radar Emitter Signal...

Area of Science:

• Electrical Engineering
• Computer Science
• Signal Processing

Background:

• Radar emitter signal recognition is crucial for electronic support measures and communication security.
• Deep learning enhances recognition accuracy but demands significant computational resources, hindering real-time, low-power applications.
• Existing research often remains experimental due to these computational constraints.

Purpose of the Study:

• To develop a resource-efficient computing acceleration platform for radar emitter signal recognition.
• To implement a 1D Convolutional Neural Network (CNN) and Long Short-Term Memory (LSTM) neural network (NN) model on Field Programmable Gate Arrays (FPGA).
• To address the limitations of high power consumption and low real-time performance in current deep learning-based radar recognition systems.

Main Methods:

• Proposed a resource reuse computing acceleration platform based on FPGA.
• Implemented a 1D-CNN-LSTM neural network model targeting intermediate frequency (IF) radar emitter signal data.
• Utilized multiplexed systolic arrays for parallel acceleration of 1D convolution and matrix-vector multiplication on FPGA.
• Evaluated the system on a Xilinx XCKU040 platform.

Main Results:

• Achieved a data throughput of 7.34 giga operations per second (GOPS).
• Maintained a low power consumption of only 5.022 W.
• Reached a high radar emitter signal recognition rate of 96.53%.
• Demonstrated significant improvements in energy efficiency ratio and real-time performance.

Conclusions:

• The FPGA-based platform effectively accelerates 1D-CNN-LSTM models for radar emitter signal recognition.
• The proposed solution overcomes computational limitations, enabling practical, low-power, real-time applications.
• This approach significantly enhances the energy efficiency and real-time capabilities of radar recognition systems.