Related Experiment Video

Updated: Apr 9, 2026

Reconfigurable Microfluidic Channel with Pin-discretized Sidewalls

Reconfigurable Microfluidic Channel with Pin-discretized Sidewalls

Published on: April 12, 2018

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory

Kaikai You¹, Lei Jin^1,2, Jianquan Jia¹

¹Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.

|February 24, 2024

Summary

This study introduces "Gate-induced drain leakage (GIDL) pre-charge" to improve 3D NAND flash reliability. This method suppresses program disturbance by enhancing channel potential without structural changes.

Area of Science:

Electrical Engineering
Semiconductor Device Physics
Materials Science

Background:

Three-dimensional (3D) vertical NAND flash memory faces reliability challenges due to program disturbance.
The narrow operational voltage window for unselected word lines (WL) exacerbates Fowler-Nordheim (FN) tunneling.
Contradictory voltage requirements for program and inhibited strings complicate disturbance suppression.

Purpose of the Study:

To investigate the relationship between channel potential and electron density in 3D NAND.
To develop a novel method for mitigating program disturbance in 3D NAND flash memory.
To enhance the reliability and operational window of 3D NAND devices.

Main Methods:

Systematic analysis of channel potential and electron density dynamics.
Introduction of a 'Gate-induced drain leakage (GIDL) pre-charge' scheme.
Validation using Technology Computer-Aided Design (TCAD) simulations and real silicon data.

Main Results:

The GIDL pre-charge method effectively enhances unselected channel potential by exploiting generated holes.
Significantly suppressed program disturbance observed in 3D NAND devices.
Demonstrated a larger pass disturb window without altering device structure or operational voltages.

Conclusions:

The GIDL pre-charge technique offers a viable solution to program disturbance in 3D NAND.
This method improves reliability without requiring new fabrication processes or modified operating parameters.
The findings provide a pathway for more robust and dependable NAND flash memory.

Keywords:

3D NAND flash GIDL pre-charge program disturbance

More Related Videos

Fabrication of Nanoheight Channels Incorporating Surface Acoustic Wave Actuation via Lithium Niobate for Acoustic Nanofluidics

Fabrication of Nanoheight Channels Incorporating Surface Acoustic Wave Actuation via Lithium Niobate for Acoustic Nanofluidics

Published on: February 5, 2020

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

Published on: May 13, 2020

Related Concept Videos

Biasing of P-N Junction

Biasing of P-N Junction

The operation of a p-n junction diode involves various biasing conditions, including forward bias, reverse bias, and equilibrium.
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...

Design Example: Capacitance Multiplier Circuit

Design Example: Capacitance Multiplier Circuit

In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.

MOSFET: Enhancement Mode

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...

Articles linked to this work by shared authors, journal, and citation graph.

Multi-Scale CNN-LSTM for Short-Circuit Fault Diagnosis of Shipboard Power System.

Sensors (Basel, Switzerland)·2026

Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory.

Micromachines·2023

Investigation of the Connection Schemes between Decks in 3D NAND Flash.

Micromachines·2023

A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory.

Micromachines·2023

LncRNA IDH1-AS1 links the functions of c-Myc and HIF1α via IDH1 to regulate the Warburg effect.

Proceedings of the National Academy of Sciences of the United States of America·2018

Endometrial thickness as a predictor of the reproductive outcomes in fresh and frozen embryo transfer cycles: A retrospective cohort study of 1512 IVF cycles with morphologically good-quality blastocyst.

Medicine·2018

See all related articles