Ferroelectric compute-in-memory annealer for combinatorial optimization problems

Area of Science:

• Materials Science
• Computer Engineering
• Computational Science

Background:

• Combinatorial optimization problems (COPs) are prevalent but computationally challenging.
• Existing solutions like digital annealers and quantum systems face limitations in scalability, memory access, and applicability.
• There is a need for efficient, scalable hardware solutions for COPs.

Purpose of the Study:

• To introduce a novel ferroelectric field-effect transistor (FeFET) based compute-in-memory (CiM) annealer.
• To demonstrate an efficient method for solving larger-scale COPs.
• To overcome the limitations of existing COP-solving hardware.

Main Methods:

• Converting COPs into quadratic unconstrained binary optimization (QUBO) formulations.
• Utilizing a three-terminal FeFET structure for in-situ vector-matrix-vector (VMV) multiplication acceleration.
• Implementing a multi-epoch simulated annealing (MESA) algorithm for efficient annealing.
• Experimental validation on a 28nm HKMG CMOS technology FeFET chip.

Main Results:

• Achieved a 75% chip size saving for Max-Cut problems due to lossless QUBO matrix compression.
• The MESA algorithm provided up to 27% better solutions and a 2X speedup compared to conventional simulated annealing.
• Demonstrated efficient in-situ acceleration of VMV operations in a single step.

Conclusions:

• The FeFET-based CiM annealer offers an efficient and scalable solution for general COPs.
• This technology shows significant promise for overcoming the limitations of current optimization hardware.
• The integrated FeFET chip represents a significant advancement in hardware acceleration for complex optimization tasks.