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Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
Donglin Lu1, Yang Chen1, Zheyi Lu1
1Key Laboratory for Micro-Nano Optoelectronic Devices of Ministry of Education, School of Physics and Electronics, Hunan University, Changsha, China.
Nature
|May 22, 2024
Summary
Researchers developed a low-temperature method for stacking 10 circuit layers using van der Waals (vdW) lamination. This technique enables monolithic three-dimensional (M3D) integration of two-dimensional (2D) semiconductors without damaging underlying components.
Area of Science:
- Materials Science
- Electrical Engineering
- Nanotechnology
Background:
- Two-dimensional (2D) semiconductors offer unique properties for monolithic three-dimensional (M3D) integration.
- Conventional high-energy microelectronic processes limit M3D integration of 2D materials due to their thinness.
- Existing methods face challenges in integrating multiple 2D circuit tiers without thermal damage.
Purpose of the Study:
- To develop a low-temperature approach for M3D integration of 2D semiconductor-based circuits.
- To overcome thermal budget limitations in fabricating multi-tier M3D integrated systems.
- To demonstrate the feasibility of van der Waals (vdW) lamination for stacking prefabricated circuit tiers.
Main Methods:
- Utilized van der Waals (vdW) lamination to integrate entire prefabricated circuit tiers.
- Controlled processing temperature to a low 120°C to protect delicate 2D materials.
- Repeated the vdW lamination process to achieve vertical stacking of multiple circuit tiers.
Main Results:
- Successfully fabricated an M3D integrated system with 10 circuit tiers in the vertical direction.
- Demonstrated that the bottom 2D transistor performance remains unaffected by the lamination process.
- Achieved functional logic and heterogeneous structures by creating vdW inter-tier vias.
Conclusions:
- The vdW lamination method provides a viable low-temperature route for M3D integration of 2D semiconductor circuits.
- This approach enables the fabrication of M3D circuits with an increased number of vertically stacked tiers.
- The technique overcomes thermal constraints, paving the way for advanced M3D electronic systems.
