Implementation of Bayesian networks and Bayesian inference using a Cu_0.1Te_0.9/HfO₂/Pt threshold switching memristor

Area of Science:

• Artificial Intelligence
• Materials Science
• Computer Engineering

Background:

• Bayesian networks and inference are crucial for AI but face hardware implementation challenges.
• Existing complementary metal oxide semiconductor (CMOS) circuits for Bayesian inference suffer from performance limitations and complexity.

Purpose of the Study:

• To propose and demonstrate a novel Bayesian network and inference circuit utilizing a volatile memristor.
• To address the limitations of conventional hardware implementations for Bayesian inference.

Main Methods:

• Development of a Bayesian network and inference circuit employing a Cu$_{0.1}$Te$_{0.9}$/HfO$_{2}$/Pt volatile memristor as a probabilistic bit neuron.
• Implementation of division feedback logic with a variational learning rate to manage device variations and suppress errors.

Main Results:

• Feasible sampling of nodal probabilities with low errors, despite memristor cycle-to-cycle variations.
• Achieved low power (<186 nW) and energy consumption (441.4 fJ) for Bayesian inference.
• Obtained a normalized mean squared error of approximately 7.5 × 10$^{-4}$.

Conclusions:

• The proposed memristor-based Bayesian network offers a power-efficient solution for AI applications.
• This approach shows potential to replace conventional CMOS-based Bayesian estimation methods.
• Stochastic computing using memristors presents a viable path for energy-efficient AI hardware.