Low-Power Analog Integrated Architecture of the Voting Classification Algorithm for Diabetes Disease Prediction

Area of Science:

• Analog integrated circuits
• Machine learning hardware
• Biomedical signal processing

Background:

• Developing energy-efficient classifiers is crucial for portable and implantable medical devices.
• Existing analog classifiers often face trade-offs between accuracy, power consumption, and feature handling capabilities.

Purpose of the Study:

• To introduce a novel, fully analog integrated architecture for a versatile voting classification algorithm.
• To demonstrate high accuracy and exceptionally low power consumption (600nW) for multi-input feature classification.

Main Methods:

• Designed a versatile voting algorithm integrating Bayes, Centroid, and Learning Vector Quantization models.
• Implemented classification models using Gaussian-likelihood, Euclidean distance, and current comparison circuits.
• Utilized TSMC 65nm CMOS technology and Cadence IC Suite for circuit design and simulation.

Main Results:

• Achieved high classification accuracy on a real-life diabetes dataset.
• Demonstrated exceptionally low power consumption of 600nW.
• Compared performance against popular analog classifiers and software-based models.

Conclusions:

• The proposed analog integrated architecture offers a promising solution for low-power, high-accuracy classification tasks.
• The versatile voting approach enhances adaptability for various input features.
• This design is suitable for resource-constrained applications, including medical diagnostics.