Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review

Area of Science:

• Digital Electronics
• Integrated Circuit Design
• FPGA Architectures

Background:

• Increasing demand for detection channels in FPGAs necessitates efficient Time-to-Digital Converters (TDCs).
• Resource utilization is a critical factor in the evolution of FPGA-based TDCs.
• Optimizing TDC performance without excessive resource consumption is a key challenge.

Purpose of the Study:

• To review principal methodologies for implementing low-resource TDCs in FPGAs.
• To outline foundational architectures and interpolation techniques for enhanced TDC performance.
• To critically assess advantages and limitations of various low-resource TDC approaches.

Main Methods:

• Review of established low-resource TDC architectures: Tapped Delay Line, Vernier Ring Oscillator, and Multi-Phase Shift Counter TDCs.
• Investigation of novel architectures including Counter Gray Oscillator TDCs.
• Analysis of interpolation techniques using Process-Voltage-Temperature stable IODELAYs and SerDes.

Main Results:

• Detailed assessment of resolution, precision, non-linearities, and resource utilization for each method.
• Identification of trade-offs between performance metrics and resource demands.
• Provision of a comprehensive summary table of existing low-resource TDC works.

Conclusions:

• Several effective low-resource TDC implementations exist for FPGAs.
• The choice of architecture depends on specific application requirements regarding performance and resource constraints.
• Advancements focus on improving resolution and stability while minimizing FPGA resource footprint.