Comprehensive analysis of faults and diagnosis techniques in cascaded multi-level inverters

Reliability is a crucial factor to consider for multi-level inverters (MLIs) used in industrial applications. With the increasing number of power semiconductor devices, the potential for defects to significantly degrade the overall system is heightened. A highly effective fault-detection technique is required to minimize the impact of faults. This paper provides a comprehensive overview of the fundamental principles of multi-level inverters and the various sorts of faults that can occur in multi-level inverters. This study provides a comprehensive analysis of five-level cascaded H-bridge multilevel inverters (MLIs) under both normal and defective conditions. The paper outlines a fault-detection method that utilizes total harmonic distortion and a normalized output voltage factor. In addition, the paper discusses a fault-isolation strategy that relies on reducing amplitude modulation. This method leads to the development of a fault-tolerant inverter. The utilization of level-shifted pulse-width modulation (LSPWM) technology is employed for the purpose of switching operations. LSPWM is the most appropriate technique for MLIs that require a low amount of computational resources. The fault-diagnosis approach given is suitable for MLI-based drives, grid-connected operations, and other applications. This paper presents a comprehensive examination of the 5L-CMLI (5-Level Cascaded Multi-Level Inverter) under various fault scenarios in CMLI. Subsequently, various fault diagnosis approaches will be examined, including their advantages and disadvantages. The paper discusses several defects that can occur in the Insulated Gate Bipolar Transistor (IGBT) of a Current Mode Logic Inverter (CMLI), and also presents a design for a reliable fault diagnosis system. Furthermore, this analysis examines several fault detection strategies in CMLI, categorized according to open-loop and closed-loop dynamic systems fault classifications.