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Phosphorus-based heterojunction tunnel field-effect transistors: from atomic insights to circuit renovations
Amir Khodabakhsh1, Amir Amini1, Arman Afzal1
1Department of Electrical Engineering, College of Technical and Engineering, West Tehran Branch, Islamic Azad University, Tehran 1461944563, Iran. Amini@wtiau.ac.ir.
Abstract:
Tunnel field-effect transistors (TFETs) are gaining interest for low-power applications, but challenges like poor drive current, delayed saturation, and ambipolarity can hinder their performance. This work proposes a dopingless heterojunction TFET (DL-HTDET) utilizing advanced materials, all based on phosphorus, to address these issues. Our approach involves a comprehensive and accurate analysis of the DL-HTDET's behavior. It employs a hybrid simulation technique integrating atomistic modeling, device simulation, and circuit design. For the first time, we use density functional theory to compute the electrical parameters of a two-dimensional material, 10-layer black phosphorus, configured in the armchair direction as the source region. InP serves as the pocket, while AlP, with its high bandgap, acts as the drain region to suppress ambipolarity. Key parameters, including bandgap, effective mass, mobility, static dielectric constant, and electron affinity, are utilized to simulate the device characteristics. Three mechanisms are considered in the device design: interband tunneling, intraband tunneling, and thermionic emission. The effect of pocket length (Lpocket) on performance is studied, and the impact of different types of interface trap charges, ranging from low to high density, is considered, and the optimized device demonstrates good durability. Additionally, the gate leakage current, which is crucial for static power consumption, is taken into account. The DC and analog/radio frequency performance of the device are evaluated. The optimized DL-HTDET achieves an ON-state current of 125 μA μm-1, a current switching ratio of 1016, an average subthreshold swing of 5.10 mV dec-1, and a transconductance of 1.47 mS μm-1. A 7T SRAM cell is implemented, demonstrating high noise margins, low delay, and ultra-low power consumption. These achievements underscore the potential of the proposed device for high-speed, ultralow power applications.
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