A 6.7 μW Low-Noise, Compact PLL with an Input MEMS-Based Reference Oscillator Featuring a High-Resolution Dead/Blind...

Area of Science:

• Electrical Engineering
• Micro-Electro-Mechanical Systems (MEMS)

Background:

• MEMS oscillators are critical for timing and frequency references.
• Conventional phase-frequency detectors (PFDs) suffer from dead/blind zones, limiting low-noise performance.
• Ultra-low-power operation is essential for portable and integrated systems.

Purpose of the Study:

• To develop an ultra-low-power phase-locked loop (PLL) for MEMS timing/frequency reference oscillator applications.
• To design a dead/blind zone-free phase-frequency detector (PFD) for enhanced low-noise performance.
• To demonstrate a high-resolution and power-efficient PLL integrated with a MEMS oscillator.

Main Methods:

• A 110.2 MHz PLL was designed using a 6.89 MHz MEMS oscillator as input.
• An ultra-low-power, high-resolution PFD without a reset feedback path was implemented.
• The PLL was fabricated using a TSMC 65 nm CMOS process.

Main Results:

• The PFD achieved a linear resolution of 100 ps with <±1.6% error and operated up to 2.5 GHz.
• The system demonstrated phase noises of -106.21 dBc/Hz at 1 kHz and -135.36 dBc/Hz at 1 MHz offset.
• The PLL consumed 6.709 μW at 1 V supply, with a frequency-normalized power consumption of 0.106 pW/Hz.

Conclusions:

• The proposed dead/blind zone-free PFD enables superior low-noise characteristics for MEMS timing references.
• The ultra-low-power PLL integrated with a MEMS oscillator offers a promising solution for advanced frequency reference applications.
• The design achieves excellent performance metrics in terms of power consumption, resolution, and phase noise.