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Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators.
Ashwin Sanjay Lele1, Bo Zhang1, Win-San Khwa2
1Corporate Research, TSMC, San Jose, California 95134, United States.
New nonvolatile memory (NVM) devices enhance artificial intelligence (AI) hardware. Optimal NVM device resistances are crucial for accurate and efficient compute-in-memory (CIM) chip performance, guiding future electronic hardware innovations.
Area of Science:
- * Exploration of advanced electronic hardware for artificial intelligence (AI) applications.
- * Focus on nonvolatile memory (NVM) devices and compute-in-memory (CIM) architectures.
Background:
- * Artificial intelligence (AI) algorithms are driving innovation in electronic hardware.
- * Nonvolatile memory (NVM) devices offer advantages in density and data retention.
- * Compute-in-memory (CIM) architectures integrate computation with AI model storage for energy efficiency.
Purpose of the Study:
- * To assess the impact of NVM device resistance on accuracy and circuit performance in CIM chips.
- * To provide recommendations for device engineers to optimize device-circuit-system interactions.
- * To review challenges in NVM device programming and benchmark existing NVM-CIM chips.
Main Methods:
- * Literature review of NVM devices and CIM architectures.
- * Analytical modeling to determine optimal device resistance bounds.
- * Benchmarking of recent NVM-CIM chip performance.
Main Results:
- * High resistance ratio and low variability in NVM devices are favored for optimal performance.
- * The low resistance state of NVM devices is constrained by accuracy and circuit performance requirements.
- * Device resistance directly influences the performance and design decisions for NVM-CIM chips.
Conclusions:
- * Frictionless device-circuit-system interactions are achievable through optimized NVM device characteristics.
- * Understanding resistance bounds is critical for designing high-performance NVM-CIM chips.
- * Future research should focus on reliable NVM device programming and advanced CIM architectures.

