Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers

High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, this work focuses on the design and implementation of closed-loop interface ASICs (Application-Specific Integrated Circuits). The proposed interface circuit, based on switched-capacitor modulation technology, incorporates a low-noise charge amplifier, sample-and-hold circuit, integrator, and clock divider circuit. To minimize average power consumption, a switched operational amplifier (op-amp) technique is adopted, which temporarily disconnects idle op-amps from the power supply. Additionally, a class-AB output stage is employed to enhance the dynamic range of the circuit. The design was realized using a standard 0.35 μm CMOS process, culminating in the completion of layout design and small-scale engineering fabrication. The performance of the MEMS accelerometers was evaluated under a 3.3 V power supply, achieving a power consumption of 3.3 mW, an accelerometer noise density below 1 μg/√Hz, a sensitivity of 1.65 V/g, a measurement range of ±1 g, a nonlinearity of 0.15%, a bandwidth of 300 Hz, and a bias stability of approximately 36 μg. These results demonstrate the efficacy of the proposed design in meeting the stringent requirements of high-precision MEMS accelerometer applications.