Design and Study of a Novel P-Type Junctionless FET for High Performance of CMOS Inverter

In this paper, a novel p-type junctionless field effect transistor (PJLFET) based on a partially depleted silicon-on-insulator (PD-SOI) is proposed and investigated. The novel PJLFET integrates a buried N+-doped layer under the channel to enable the device to be turned off, leading to a special work mechanism and optimized performance. Simulation results show that the proposed PJLFET demonstrates an I_on/I_off ratio of more than seven orders of magnitude, with I_on reaching up to 2.56 × 10^-4 A/μm, I_off as low as 3.99 × 10^-12 A/μm, and a threshold voltage reduced to -0.43 V, exhibiting excellent electrical characteristics. Furthermore, a new CMOS inverter comprising a proposed PJLFET and a conventional NMOSFET is designed. With the identical geometric dimensions and gate electrode, the pull-up and pull-down driving capabilities of the proposed CMOS are equivalent, showing the potential for application in high-performance chips in the future.