Hardware Accelerator for a Power Efficient Single-lead Dry-electrode ECG Wearable Design

Area of Science:

• Biomedical Engineering
• Wearable Technology
• Signal Processing

Background:

• Single-lead electrocardiographic (ECG) wearables are promising for remote monitoring.
• High power consumption in current wearables limits battery life due to complex pre-processing.
• Dry electrode integration presents challenges for long-term ECG monitoring.

Purpose of the Study:

• To propose a novel hardware (HW) architecture for dry electrode-based ECG signal processing.
• To improve the longevity of wearable ECG monitoring devices.
• To enable efficient, real-time signal processing for remote health applications.

Main Methods:

• Developed an analog-front end (AFE) chip combined with a Field Programmable Gate Array (FPGA).
• Implemented an optimized cubic Hermite interpolation algorithm on the FPGA for signal processing.
• Deployed the system on an FPGA board with a single-core processor, focusing on low power consumption.

Main Results:

• The proposed architecture achieved low power consumption (0.01 W).
• It utilized minimal FPGA resources (0.67% LUTs, 0.44% FFs) for real-time processing.
• Achieved an average signal-to-noise ratio (SNR) of 16.4 dB with computed Signal Quality Indexes (SQIs).

Conclusions:

• The developed HW architecture significantly enhances wearable ECG monitoring longevity.
• It provides efficient, real-time signal processing suitable for dry electrode applications.
• The system is effective for heart rate (HR) and heart rate variability (HRV) estimations in long-term monitoring.