A Compact Device Model for a Piezoelectric Nano-Transistor.

Area of Science:

• Micro-electronics Engineering
• Computational Modeling
• Materials Science

Background:

• Investigating micro-electronic devices like nano-scaled piezoelectronic transistors requires efficient design space exploration.
• Fast, approximate models are valuable for initial performance estimations in complex device design.

Purpose of the Study:

• To develop and verify an approximate compact model for micro-electronic devices, specifically nano-scaled piezoelectronic transistors.
• To assess the model's utility in exploring the initial design space and reducing the need for extensive simulations.

Main Methods:

• Development of an approximate compact model for micro-electronic devices.
• Verification of the compact model against accurate axi-symmetric finite element analysis (FEA).
• Comparison of model predictions under two sets of boundary and interface conditions: one replicating analytical behavior and another simulating practical device operation.

Main Results:

• The compact model showed high accuracy (order 10⁻⁴ to 10⁻⁵ difference) when compared to FEA for both RF switches and VLSI devices under specific verification conditions.
• Under relaxed, practical conditions, the compact model demonstrated good agreement for RF switches with thin piezoelectric layers, suggesting design space reduction potential.
• For VLSI devices under practical conditions, the compact model exhibited significant errors, indicating its limitations for complex systems.

Conclusions:

• The developed compact model is a valuable tool for initial design space exploration of RF switches, offering fast and reliable estimates.
• The compact model's accuracy diminishes for VLSI devices under practical operating conditions, where precise finite element analysis (FEA) remains essential.
• The study highlights the trade-offs between model simplicity and accuracy, guiding the selection of appropriate simulation methods for different micro-electronic devices.