A Compact Device Model for a Piezoelectric Nano-Transistor

An approximate compact model was developed to provide a convenient method of exploring the initial design space when investigating the performance of micro-electronic devices such as nano-scaled piezoelectronic transistors, where fast ball-park estimates can be very helpful. First of all, the compact model was verified by comparing its predictions with those of accurate axi-symmetric finite element analysis (FEA) using special boundary and interface conditions that enable the replication of the analytical model behaviour. Verification is achieved for a radio frequency (RF) switch and a smaller very-large-scale integrated (VLSI) device, where percentage differences between the compact and FEA model predictions are of the order 10^-4 for the RF switch and 10^-5 for the VLSI device. This confirms the consistency of complex property data (especially electro-thermo-elastic constants) and geometrical parameter input to both types of models and convincingly demonstrates that the analytical models and FEA for the two devices have been implemented correctly. A second type of boundary and interface condition is also used that is designed to replicate the actual behaviour of the devices in practice. The boundary and interface constraints applied for the verification procedure are relaxed so that there is perfect interface bonding between layers. For this unconstrained case, the resulting deformation is very complex, involving both bending effects and edge effects arising from property mismatches between neighbouring layers. The results for the RF switch show surprisingly good agreement between the predictions of the analytical and FEA results, provided the thickness of the piezoelectric layer is not too thick, implying that the analytical model should help to reduce the parameter design space for such devices. However, for the VLSI device, our results indicate that the compact model leads to much larger errors. For such systems, the compact model is unlikely to be able to reliably reduce the parameter design space, implying that accurate FEA will then need to be used.