Logic and static memory functions of an inverter comprising a feedback field effect transistor

Area of Science:

• Semiconductor device physics
• Nanoelectronics
• Computer architecture

Background:

• The von Neumann architecture faces performance limitations due to the CPU-memory speed gap, causing high power consumption.
• Feedback field-effect transistors (FBFETs) show promise for next-generation electronics due to their unique switching characteristics.

Purpose of the Study:

• To configure and simulate logic and static memory functions of an inverter using an n-channel FBFET.
• To evaluate the performance of FBFET-based inverters for high-speed, low-power applications.

Main Methods:

• Mixed-mode simulation of an inverter circuit.
• Utilizing a silicon-on-insulator (SOI) based p-n-p-n FBFET with 30 nm channel length.
• Characterization of on/off current ratio and subthreshold swing.

Main Results:

• Achieved an on/off current ratio of approximately 10^11 and subthreshold swing below 5.4 mV/dec.
• Demonstrated logic operations and static memory functions including fast write, long hold, and non-destructive read.
• Inverter operation exhibited nanosecond-level speed and non-destructive read stability exceeding 100 seconds.

Conclusions:

• The proposed n-FBFET-based inverter successfully integrates logic and memory functions.
• This technology presents a promising solution for overcoming the von Neumann bottleneck in future high-speed, low-power computing systems.