A 9.68nW 57.51dB SNDR SAR ADC With Dual Bypass Windows Based on Non-Binary Split Capacitors for Biomedical...

The paper proposes a low-power Successive Approximation Register (SAR) Analog-to-Digital Conversion (ADC) with dual bypass windows based on non-binary split capacitors. To reduce the power consumption, the bypass windows constituted by the split capacitors can maximize the coverage of biological signals both in the resting state and excited state. When the signal falls within the designated window, unnecessary conversion cycles are skipped. This process is mainly judged and controlled by digital circuits, which is highly robust and does not require calibration. Meanwhile, a low-power dynamic CMOS comparator is proposed, which can effectively reduce the voltage variation of the latch node during the comparator's operation, further reducing power consumption. The proposed SAR ADC, based on a 180nm process, measures a power consumption of 9.68nW at a supply voltage of 0.6V and a sampling rate of 5.21kS/s. The signal-to-noise-and-distortion ratio (SNDR) and the spur-free dynamic range (SFDR) are measured at 57.51dB and 71.68dB, respectively. It also achieves an effective number of bits (ENOB) of 9.26 bits and a Walden figure-of-merit (FoM) of 2.9 fJ/conv.-step. The proposed SAR ADC is also verified by collected electromyogram (EMG), electrocardiogram (ECG), and electroencephalogram (EEG) signals. The average power consumption for quantifying EMG signals is 7.95 nW, providing an attractive solution for low-power SAR ADCs in biomedical applications.