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Updated: Jun 23, 2026

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots
Published on: November 1, 2013
Bell inequality violation in gate-defined quantum dots
Paul Steinacker1, Tuomo Tanttu2,3, Wee Han Lim2,3
1School of Electrical Engineering and Telecommunications, University of New South Wales, Sydney, NSW, 2052, Australia. p.steinacker@unsw.edu.au.
Abstract:
Quantum computers leverage entanglement to achieve superior computational power. However, verifying that the entangled state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. While low error rates for state preparation, control, and measurement have been independently demonstrated, a simultaneous demonstration remained challenging. We employ advanced protocols like heralded initialization and calibration via gate set tomography (GST), to push fidelities of the full 2-qubit gate set above 99%, including state preparation and measurement (SPAM). We demonstrate a 97.17% Bell state fidelity without correcting for readout errors and violate Bell's inequality using direct parity readout with a Bell signal of S = 2.731. Our measurements exceed the classical limit even at 1.1 K or entanglement lifetimes of 100 μs. Violating Bell's inequality in a silicon quantum dot qubit system is a key milestone, as it proves quantum entanglement, fundamental to achieving quantum advantage.
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